An EEPROM (Electronically Erasable and Programmable Read Only Memory) is widely known as a kind of a nonvolatile memory in which data can electrically be written, erased and read. A flash memory (flash type EEPROM) is a representative example.
The flash memory includes a MOS (Metal Oxide Semiconductor) transistor including a source region and a drain region formed on a semiconductor substrate, a gate insulator formed between the source region and the drain region on the semiconductor substrate 100, a floating gate formed on the gate insulator, an insulation thin film formed on the floating gate, and a control gate formed on the insulation thin film.
In order to write data in the flash memory, a source terminal is brought into a ground level, predetermined voltage is applied to a drain terminal and a gate terminal to generate potential difference between the drain region and the floating gate, negative charge (electrons) is accumulated in the floating gate through the gate insulator by the potential difference, continuity of channel of the MOS transistor is varied, thereby recording data.
On the other hand, in order to erase data written in the flash memory, the drain terminal is opened, the gate terminal is brought into the ground level, voltage higher than normal level is applied to the source terminal to generate potential difference between the source region and the floating gate, accumulated negative charge (electrons) on the floating gate is pulled out to the source terminal through the gate insulator.
However, if the writing and erasing operations of data, i.e., charging and pulling-out operations of electrons into and from the floating gate are repeated many times, this operations forcibly passes the electrons through the insulator, and the insulator is gradually deteriorated and a faulty cell in which data can not be recorded is generated. A nonvolatile memory is usually constituted as a memory cell array in which plural blocks including cells of plural bits are arranged, and of the memory cell array, even a single faulty cell is generated, the lifetime of the memory cell expires.
The lifetime of the memory cell is usually about several tens of thousand, but the lifetime is largely varied. It is not easy to tell remaining lifetime of the memory cell, and various determining methods of the lifetime are conventionally proposed. For example, there is proposed a technique in which a rewriting time counter for counting the number of rewriting times of data for each block of memory cell array, a memory portion in which the count value is stored, and a control circuit for controlling the number of rewriting times counting operation, the storing operation, the erasing operation and the reading operation are prepared, and it is determined that a memory cell of a block whose count value reaches a predetermined value is deteriorated (see Patent Document 1, for example). However, since clear correlation does not exist between the number of rewriting times of data and deterioration of the memory cell generated by rewriting of data, the remaining lifetime of the memory cell cannot be determined precisely by the method of the Patent Document 1.
There is disclosed a deterioration detecting method of a memory cell in which erasing time measuring means for measuring erasing time elapsed until information written in a memory cell is erased, a reference erasing time memory for storing preset reference erasing time, and deterioration detecting means for detecting deterioration of the memory cell by comparing the measured erasing time and the preset reference erasing time with each other are used (see Patent Document 2, for example).
In the method of the Patent Document 2, since high correlation does not exist between the erasing time of information and deterioration of a memory cell, the remaining lifetime of the memory cell cannot be accurately determined.
Patent Document 1: Japanese Laid-open Patent Publication No. H6-223590
Patent Document 2: Japanese Laid-open Patent Publication No. 2002-208286
In view of the above circumstances, it is an object of the present invention to provide a nonvolatile memory capable of precisely determining a remaining lifetime of a memory cell.